Migrating MMIO from a source I/O adapter of a computing system to a destination I/O adapter of the computing system

ABSTRACT

Migrating MMIO from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, MMIO mapping information, wherein the hypervisor supports operation of a logical partition executing and the logical partition is configured for MMIO operations with the source I/O adapter through a MMU of the computing system utilizing the MMIO mapping information; placing, by the hypervisor, the destination I/O adapter in an error state; configuring, by the hypervisor, the MMU for MMIO with the logical partition utilizing the MMIO mapping information collected by the hypervisor; and enabling the destination I/O adapter to recover from the error state.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of and claims priority from U.S. patent application Ser. No. 15/299,512, filed Oct. 21, 2016.

BACKGROUND

Field of the Invention

The field of the invention is data processing, or, more specifically, methods, apparatus, and products for migrating MMIO.

Description of Related Art

A logical partition may be configured to utilize a physical, rather than virtual, I/O adapter. Such a configuration may rely on direct memory access operations between the I/O adapter. In current server-class systems there are large I/O fabrics incorporating many layers of bridge chips, switches, and I/O devices. The I/O devices themselves may be further virtualized in technologies such as SR-IOV. A memory mapped I/O (MMIO) access request generated by a logical partition must properly traverse this fabric and be delivered to the I/O device.

The routing and handling of the MMIO accesses involve both hardware configuration and software configuration across many layers of the system including the hypervisor and the logical partition. The logical partition is made directly aware of the MMIO address mappings which are associated with specific I/O devices. Any changes to these relationships require the updated configuration mappings to be communicated across all parties. This limits both configuration flexibility and the ability to reconfigure (for example, due to hardware failure or resource movement).

SUMMARY

Methods, apparatus, and products for migrating memory mapped input/output (‘MMIO’) from a source input/output (‘I/O’) adapter of a computing system to a destination I/O adapter of the computing system are disclosed in this specification. Such migration may be carried out by: collecting, by a hypervisor of the computing system, MMIO mapping information, where the hypervisor supports operation of a logical partition executing and the logical partition is configured for MMIO operations with the source I/O adapter through a memory management unit (‘MMU’) of the computing system utilizing the MMIO mapping information; placing, by the hypervisor, the destination I/O adapter in an error state; configuring, by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information collected by the hypervisor; and enabling the destination I/O adapter to recover from the error state.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 sets forth an example system configured for migrating MMIO according to embodiments of the present invention.

FIG. 2 sets forth a functional block diagram of an example system configured for MMIO migration according to embodiments of the present invention.

FIG. 3 sets forth a set of example MMIO mapping data structures in the form of several tables.

FIG. 4 sets forth a flow chart illustrating an exemplary method for migrating MMIO from a source I/O adapter of a computing system to a destination I/O adapter of the computing system according to embodiments of the present invention.

FIG. 5 sets forth a flow chart illustrating a further exemplary method for MMIO migration according to embodiments of the present invention.

FIG. 6 sets forth a flow chart illustrating a further exemplary method for MMIO migration according to embodiments of the present invention.

FIG. 7 sets forth a flow chart illustrating a further exemplary method for MMIO migration according to embodiments of the present invention.

DETAILED DESCRIPTION

Embodiments of methods, apparatus, and computer program products for migrating MMIO from a source I/O adapter of a computing system to a destination I/O adapter of the computing system are described with reference to the accompanying drawings, beginning with FIG. 1. FIG. 1 sets forth an example system configured for migrating MMIO according to embodiments of the present invention. The example of FIG. 1 includes a data center (120). Such a data center may provide clients on host devices (195) with virtualization services for enabling various cloud related product offerings.

The example data center (120) of FIG. 1 includes automated computing machinery in the form of a computing system (102) configured for migrating MMIO from a source I/O adapter to a destination I/O adapter according to embodiments of the present invention. One example type of I/O adapter that may be configured for such MMIO migration is an SR-IOV adapter. Readers will recognize that such SR-IOV adapters are only an example of a type of I/O adapter and that many different types of I/O adapters may be configured for MMIO migration according to embodiments of the present invention. SR-IOV, Single-root I/O virtualization, is an extension to the PCI Express (PCIe) specification. SR-IOV allows a device, such as a network adapter, to separate access to its resources among various PCIe hardware functions. These functions consist of the following types: A PCIe Physical Function (PF) and a PCIe Virtual Function (VF). The PF advertises the device's SR-IOV capabilities. Each VF is associated with a device's PF. A VF shares one or more physical resources of the device, such as a memory and a network port, with the PF and other VFs on the device. From the perspective of a logical partition (116, 118) instantiated by a hypervisor (136), a VF appears as a fully functional physical PCIe adapter. In this way, a single physical adapter may be ‘shared’ amongst many logical partitions or multiple virtual functions may be instantiated for use by a single logical partition.

The computing system (102) includes at least one computer processor (156) or “CPU” as well as random access memory (168) or “RAM,” which is connected through a high speed memory bus (166) and bus adapter (158) to processor (156) and to other components of the computing system (102).

Stored in RAM (168) is a hypervisor (136) and a management console (138). The management console (138) may provide a user interface through which a user may direct the hypervisor (136) on instantiating and maintaining multiple logical partitions (116, 118), where each logical partition may provide virtualization services to one or more clients. The management console (138) may also administer the migration of MMIO from the source I/O adapter of the source computing system to a destination I/O adapter.

Also stored in RAM (168) are two instances of an operating system (154), one for each logical partition (116, 118). Operating systems useful in computers configured for MMIO migration according to various embodiments include UNIX™, Linux™, Microsoft Windows™, AIX™, IBM's i™ operating system, and others as will occur to those of skill in the art. The operating systems (154), hypervisor (136), and management console (138) are shown in RAM (168), but many components of such software may typically be stored in non-volatile memory such as, for example, on a data storage (170) device or in firmware.

The computing system (102) may also include a storage device adapter (172) coupled through expansion bus (160) and bus adapter (158) to processor (156) and other components of the computing system (102). Storage device adapter (172) connects non-volatile data storage to the computing system (102) in the form of data storage (170). Storage device adapters useful in computers configured for MMIO migration according to various embodiments include Integrated Drive Electronics (“IDE”) adapters, Small Computing system Interface (“SCSI”) adapters, and others as will occur to those of skill in the art. Non-volatile computer memory also may be implemented as an optical disk drive, electrically erasable programmable read-only memory (so-called “EEPROM” or “Flash” memory), RAM drives, and so on, as will occur to those of skill in the art.

The example computing system (102) may also include one or more input/output (“I/O”) adapters (178). I/O adapters implement user-oriented input/output through, for example, software drivers and computer hardware for controlling output to display devices such as computer display screens, as well as user input from user input devices (181) such as keyboards and mice. The example computing system (104) may also include a video adapter (114), which may be an example of an I/O adapter specially designed for graphic output to a display device (180) such as a display screen or computer monitor. Video adapter (114) may be connected to processor (156) through a high speed video bus (164), bus adapter (158), and the front side bus (162), which may also be a high speed bus.

The example computing system (102) of FIG. 1 also includes several I/O adapters which may be implemented as SR-IOV adapters in the form of network adapters (124, 126, and 128). Any of the example network adapters from among network adapters (124, 126, and 128) may be configured to support SR-IOV and provide multiple virtual functions, where each of the virtual functions may be mapped to a respective logical partition (116, 118). In this way, each of the logical partitions may independently use a physical network adapter that is being shared among different logical partitions. Such network adapters may also be configured for data communications with other computers or devices (not shown) and for data communications with a data communications network (100). Such data communications may be carried out serially through RS-232 connections, through external buses such as a Universal Serial Bus (“USB”), through PCI and PCIe fabrics, through data communications networks such as IP data communications networks, and in other ways as will occur to those of skill in the art. Network adapters may implement the hardware level of data communications through which one computer sends data communications to another computer, directly or through a data communications network. Examples of communications adapters useful in computers configured for MMIO migration according to various embodiments include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

The network adapters (124, 126, and 128) may further be configured for data communications with hosts (195) over a network (101) reachable through local area networks (LANs), such as LAN (100). The network adapters (124, 126, and 128) may further be configured for data communications with storage area networks (SANs), such as SAN (112), and for data communications with various storage devices, such as storage devices (106) and storage devices (108).

From time to time and for various reasons, it may be necessary or preferred to switch an I/O adapter coupled to a logical partition to another I/O adapter of the same computing system (102). Such a switching is referred to in this specification as migration. In prior art embodiments in which the logical partition is coupled to an I/O adapter through a physical communication channel (rather than an entirely virtualized communications channel), the I/O adapter must be deconfigured from the logical partition completely prior to migration. Another I/O adapter would then be added to the logical partition as if a new adapter were added to the system. Further, in some embodiments, the logical partition and I/O adapter are configured for MMIO. A logical partition migration that requires the deconfiguring of an I/O device and an addition of a new I/O device would generally require a complete reconfiguration of MMIO.

When configuring a logical partition (116) for MMIO with a source I/O adapter, the hypervisor, upon instantiation of the logical partition may create or modify are hardware page table (142) in a memory management unit (MMU) (140) with MMIO mapping information, among other address mappings. The logical partition is configured with logical addresses for MMIO. Such logical addresses appear to the logical partition as real physical memory addresses, but do not actually reference a physical memory location directly. Instead, the logical addresses must be translated into physical addresses. The hardware page table (142) may include entries that associate a logical address assigned to a logical partition to a physical address. Readers of skill will recognize that many other data structures and layers of abstraction may exist as well. The MMU receives a logical address as part of an MMIO operation initiated by the logical partition on the memory bus (166), translates the logical address to a physical address and generates an I/O transaction on the expansion bus (160) directed to the I/O adapter coupled to the logical partition for MMIO. In switching from one I/O adapter to another I/O adapter, the mappings from logical addresses to physical addresses will not be correct. Completely reconfiguring the logical partition after migration with a new I/O adapter, MMIO, and new logical addresses injects downtime into the migration process.

To that end, the computing system (102) of FIG. 1 may be configured for migrating MMIO from a source I/O adapter of the computing system (102) to a destination I/O adapter of the computing system. Such migration may include: collecting, by the hypervisor (136) of the computing system (102), MMIO mapping information (142) from the MMU (140); placing, by the hypervisor (136), the destination I/O adapter in an error state; configuring, by the hypervisor (136), the MMU (142) for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information (142) collected by the hypervisor (136); and enabling the destination I/O adapter to recover from the error state. In this way, the logical partition maintains the logical addresses originally assigned to it for MMIO after migration to the destination I/O adapter.

Examples of such an I/O adapter may be the network adapters (124, 126, and 128) of FIG. 1. The network adapters (124, 126, and 128) are for purposes of illustration, not for limitation. Similarly, data centers according to various embodiments may include additional servers, routers, other devices, and peer-to-peer architectures, not shown in the figures, as will occur to those of skill in the art. Networks in such data processing systems may support many data communications protocols, including for example TCP (Transmission Control Protocol), IP (Internet Protocol), HTTP (HyperText Transfer Protocol), WAP (Wireless Access Protocol), HDTP (Handheld Device Transport Protocol), and others as will occur to those of skill in the art. Various embodiments may be implemented on a variety of hardware platforms in addition to those illustrated.

The arrangement of servers and other devices making up the exemplary system illustrated in FIG. 1 are for explanation, not for limitation. Data processing systems useful according to various embodiments of the present invention may include additional servers, routers, other devices, and peer-to-peer architectures, not shown in FIG. 1, as will occur to those of skill in the art. Networks in such data processing systems may support many data communications protocols, including for example TCP (Transmission Control Protocol), IP (Internet Protocol), HTTP (HyperText Transfer Protocol), WAP (Wireless Access Protocol), HDTP (Handheld Device Transport Protocol), and others as will occur to those of skill in the art. Various embodiments of the present invention may be implemented on a variety of hardware platforms in addition to those illustrated in FIG. 1.

For further explanation, FIG. 2 sets forth a functional block diagram of an example system configured for MMIO migration according to embodiments of the present invention. The example system of FIG. 2 includes a management console (226). A management console may be implemented as a module of automated computing machinery comprising computer hardware and software. The management console (226) may be coupled to the computing system (202) through various networking devices, protocols, and fabrics. The management console may provide a user interface through which a user may direct the hypervisor (206) on instantiating and maintaining logical partitions, where each logical partition may provide virtualization services to one or more clients. The management console (226) may also direct hypervisors to migrate logical partitions from one computing system to another computing system or to migrate from one I/O adapter (212) to another (224).

In the example of FIG. 2, the computing system (202) is a computing system similar that depicted in the example of FIG. 1. The computing system (202) includes a source (212) and destination I/O adapter (224). The term ‘source’ is used here solely to denote that the I/O adapter is the origin of a migration of MMIO. Likewise, the term ‘destination’ is utilized merely to indicate that the destination I/O adapter (224) is a target of a migration of MMIO.

The example computing system (202) of FIG. 2 include a hypervisor (206) that supports execution of at least one logical partition (204). The logical partition is coupled to a source I/O adapter (212) for I/O operations. Upon instantiation of the logical partition, the source hypervisor (206) creates or modifies a hardware page table (208) in the MMU (210) of the computing system. The hardware page table (208) includes mappings of logical addresses assigned to the logical partition (sometimes referred to as “LPAR logical addresses”) to physical addresses.

In the example of FIG. 2, the management console (226) initiates a migration of I/O adapters. One obstacle to such a migration in the prior art is the existence of MMIO mappings between the logical partition and the source I/O adapter. In prior art systems, the source I/O adapter must be deconfigured from the system, essentially removing all MMIO mappings entirely, prior to the logical partition being migrated. The LPAR logical addresses are removed in such deconfiguration. A new I/O adapter would be added to the system and the logical partition would be required to create new MMIO mappings for the new I/O adapter, that is, new LPAR logical addresses would need to be assigned.

By contrast, the system of FIG. 2 is configured for MMIO migration according to embodiments of the present invention. The management console (226) may orchestrate the migration between I/O adapters by first instructing the hypervisor (206) to prepare for the migration. The hypervisor (206), among other operations to prepare for the I/O migration, may collect MMIO mapping information. Collecting such MMIO mapping information may be carried out by collecting a PCI configuration space address of the source I/O adapter; collecting the PCI memory address of the source I/O adapter; and collecting, from the hardware page table (208) of the MMU (210), LPAR logical memory addresses mapped to physical real addresses for MMIO. The PCI configuration space address is utilized to address the configuration space of a PCI adapter. Such an address may also be referred to as a requester identifier or (‘RID’). In PCI-express architectures, each PCI device under a root complex is uniquely identified by such an RID. The RID may be a triplet of a bus number, device number, and function number. Such attributes may be assigned to the PCI adapter upon initialization and enumeration of the device in the system and be located in the configuration space of a PCI adapter. The RID may be used to control access to memory or other resources in the system. Such an RID may be utilized as an index into one or more data structures of the MMU or hypervisor that maintains MMIO mapping information.

The hypervisor (206) may also be instructed by the management console (226) to prepare for the migration by collecting physical real addresses utilized to route MMIO operations to memory space of the destination I/O adapter. Such addresses will be later mapped to the LPAR logical address assigned for MMIO.

The management console (226) may also instruct the destination hypervisor (218) to place the destination I/O adapter (224) in an error state. Such an error state may include the ‘EEH’ (enhanced error handling) error state which is an extension to the PCI standard specification and enabled in systems running IBM's Power™ Processors.

The management console may then configure the MMU (210) for MMIO between the destination I/O adapter and the logical partition utilizing the MMIO mapping information collected by the hypervisor. Such configuration may include: inserting in the hardware page table (208) of the MMU (210) mappings of the LPAR logical memory addresses collected by the hypervisor (206) to the physical real addresses utilized to route MMIO operations to memory space of the destination I/O adapter (224).

Finally, the management console may instruct the hypervisor to enable the destination I/O adapter to recover from the error state. Enabling the logical partition and destination I/O adapter to recover from the error state may be carried out in various ways including injecting a command on the I/O adapter bus designated for such a purpose, setting or removing a flag at a particular location in I/O adapter memory and logical partition memory designated for such purpose, or otherwise informing an I/O adapter driver of the logical partition that recovery can proceed. The logical partition maintains the LPAR logical addresses assigned for MMIO with the source I/O adapter (212) after migration to the destination I/O adapter. Further, the logical partition (204) may perform MMIO operations by utilizing the same LPAR logical addresses.

As mentioned above, in some embodiments, specifically in embodiments in which the I/O adapter is implemented as a PCIe adapter or SR-IOV adapter, the MMIO mapping information collected by the source hypervisor and utilized to update mapping information for the destination I/O adapter may be implemented as one or more data structures including a hardware page table. For further explanation, therefore, FIG. 3 sets forth a set of example MMIO mapping data structures in the form of several tables.

The example of FIG. 3 includes an MMU (312). Such an MMU may be a component of a processor or a stand alone component. The MMU includes a hardware page table (308) and a PCI address table (310). The hardware page table (308) may be created or modified upon instantiation of a logical partition. The hardware page table includes a number of entries, with each entry associating a logical address known to and utilized by a logical partition (302). The logical address may be in the form of a real memory address, but in fact does not refer to an actual physical memory location. Instead, the logical address must be translated by the MMU, through use of the hardware page table (308), into a physical real address. Although only a single hardware page table is depicted for ease of explanation, readers of skill in the art will recognize that additional data structures with additional layers of address abstraction may be utilized in translating a logical address to a real address.

In the example of FIG. 3, the logical partition (302) has initiated an MMIO operation (306) via the memory bus (304). The MMIO operation (306) includes, among other attributes not shown, a logical address known to the logical partition as well as an I/O commend. The MMU, translates the logical address into a physical real address utilizing the hardware page table (308).

The MMU may then generate a PCI transaction (318) through the PCI fabric (314), by identifying the PCI address associated with the physical real address through use of the PCI address table (310). The PCI address table (310) includes entries, each of which in turn includes an association of a physical real address to a PCI address. The PCI address is utilized to address the I/O adapter (316) through the PCI bus. To that end, the MMU generates the PCI transaction (318) with the PCI address and the I/O command from the original MMIO operation (306) and places the PCI transaction (318) on the bus.

Readers will understand that the example of FIG. 3 is brief for purposes of clarity. The example, however, does highlight that the logical partition (302) is aware only of the logical addresses provided to it for MMIO operations. When the logical partition is migrated from one I/O adapter to another, the logical partition in embodiments of the present invention may maintain the same LPAR logical addresses for MMIO. In order to maintain such logical addresses, the translation of the logical addresses must be updated in the hardware page table and the PCI address table. Thus, when the hypervisor collects MMIO information, the contents of the hardware page table (308), at least with respect to the logical addresses assigned to the logical partition, are collected and later used to map to the destination I/O adapter real addresses in the hardware page table.

For further explanation, FIG. 4 sets forth a flow chart illustrating an exemplary method for migrating MMIO from a source I/O adapter of a computing system to a destination I/O adapter of the destination computing system according to embodiments of the present invention. In the method of FIG. 4, the computing system includes a hypervisor that supports operation of a logical partition and the logical partition is configured for MMIO operations with the source I/O adapter through an MMU of the source computing system.

The method of FIG. 4 includes collecting, by a hypervisor of the computing system, MMIO mapping information. In embodiments in which the source and destination I/O adapter are implemented as PCI, PCIe, or SRIOV adapters, collecting (402) MMIO mapping information may be carried out by: collecting a PCI configuration space address of the source I/O adapter; collecting the PCI memory address of the source I/O adapter; and collecting, from a hardware page table of the MMU of the computing system, LPAR logical memory addresses mapped to physical real addresses for MMIO.

The method of FIG. 4 also includes placing (404), by the hypervisor, the destination I/O adapter in an error state. Placing (404) the destination I/O adapter in an error state may be carried out by setting one or more flags in a register of the destination I/O adapter designated for such purpose, sending a message to the I/O adapter on the bus that indicates an error has arisen, and in other ways as will occur to readers of skill in the art. Such an error state may include the ‘EEH’ (enhanced error handling) error state which is an extension to the PCI standard specification and enabled in systems running IBM's Power™ Processors.

The method of FIG. 4 also includes configuring (406), by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O utilizing the MMIO mapping information collected by the hypervisor. In some embodiments, configuring (406) the MMU for MMIO between the logical partition and the destination I/O may include updating the hardware page tables with mappings of physical addresses of the destination I/O to the LPAR logical address used for MMIO with the source I/O adapter.

The method of FIG. 4 also includes enabling (408) the destination I/O adapter to recover from the error state and couple to the logical partition as if the two had been previously coupled. Enabling (408) the destination I/O adapter to recover from the error state may be carried out in various ways including injecting a command on the I/O adapter bus designated for such a purpose, setting or removing a flag at a particular location in I/O adapter memory and logical partition memory designated for such purpose, or otherwise informing an I/O adapter driver of the logical partition that recovery can proceed. The logical partition maintains the LPAR logical addresses assigned for MMIO with the source I/O adapter after migration to the destination I/O adapter. Further, the logical partition (204) may perform MMIO operations by utilizing the same LPAR logical addresses.

For further explanation, FIG. 5 sets forth a flow chart illustrating a further exemplary method for MMIO migration according to embodiments of the present invention. The method of FIG. 5 is similar to the method of FIG. 4 in that the method of FIG. 5 is also carried out in a computing system that includes a source I/O adapter, destination I/O adapter, a hypervisor, an MMU, and a logical partition that is coupled for MMIO to the source I/O adapter through MMIO mappings stored in the MMU. The method of FIG. 5 is also similar to the method of FIG. 5 in that the method of FIG. 5 includes: collecting (402), by a hypervisor of the computing system, MMIO mapping information; placing (404), by the hypervisor, the destination I/O adapter in an error state; configuring (406), by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information collected by the hypervisor; and enabling (408) the destination I/O adapter to recover from the error state.

The method of FIG. 5 differs from the method of FIG. 4, however, in that in the method of FIG. 5, the source and destination I/O adapters are implemented as PCI adapters. A PCI adapter as the term is used here encompasses any type of PCI, including, but not limited to, PCIe or SR-IOV. To that end, the method of FIG. 5 includes collecting (502) physical real addresses utilized to route MMIO operations to memory space of the destination I/O adapter. Such a collection of physical real addresses may be carried out in various ways including, for example, by querying the hardware page table for physical real addresses assigned to the logical partition and mapped to the destination I/O adapter, querying the configuration space of the destination I/O adapter for addresses assigned to the adapter upon its enumeration in the system, and so on as will occur to readers of skill in the art.

In the method of FIG. 5, configuring (406) the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information collected by the hypervisor is carried out by inserting (504), in the hardware page table of the MMU, mappings of the LPAR logical memory addresses collected by the hypervisor to the physical real addresses utilized to route MMIO operations to memory space of the destination I/O adapter. That is, the addresses of the destination I/O adapter are mapped to the logical partition memory addresses provided in the MMIO mapping information by the source hypervisor.

For further explanation, FIG. 6 sets forth a flow chart illustrating a further exemplary method for MMIO migration according to embodiments of the present invention. The method of FIG. 6 is similar to the method of FIG. 4 in that the method of FIG. 6 is also carried out in a computing system that includes a source I/O adapter, destination I/O adapter, a hypervisor, an MMU, and a logical partition that is coupled for MMIO to the source I/O adapter through MMIO mappings stored in the MMU. The method of FIG. 6 is also similar to the method of FIG. 6 in that the method of FIG. 6 includes: collecting (402), by a hypervisor of the computing system, MMIO mapping information; placing (404), by the hypervisor, the destination I/O adapter in an error state; configuring (406), by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information collected by the hypervisor; and enabling (408) the destination I/O adapter to recover from the error state.

The method of FIG. 6 differs from the method of FIG. 4 in that the method of FIG. 6 also includes placing (602), by the hypervisor, the source I/O adapter in an error state, thereby quiescing MMIO traffic to the source I/O adapter. Placing (602) the source I/O adapter in an error state may include placing the adapter in an EEH freeze state. Upon being in the freeze state, outstanding MMIO operations will be quiesced and essentially flushed from the pipeline. In this way, when the logical partition is migrated from the source to the destination I/O adapter, the logical partition will not have pending MMIO operations outstanding for the source I/O adapter which cannot be completed because the logical partition is no longer coupled to the source I/O adapter.

The method of FIG. 6 also includes deconfiguring (604) the source I/O adapter from the computing system. Deconfiguring (604) the source I/O adapter from the computing system may include removing the source I/O adapter from the device tree of the computing system.

For further explanation, FIG. 7 sets forth a flow chart illustrating a further exemplary method for MMIO migration according to embodiments of the present invention. The method of FIG. 7 is similar to the method of FIG. 4 in that the method of FIG. 7 is also carried out in a computing system that includes a source I/O adapter, destination I/O adapter, a hypervisor, an MMU, and a logical partition that is coupled for MMIO to the source I/O adapter through MMIO mappings stored in the MMU. The method of FIG. 7 is also similar to the method of FIG. 7 in that the method of FIG. 7 includes: collecting (402), by a hypervisor of the computing system, MMIO mapping information; placing (404), by the hypervisor, the destination I/O adapter in an error state; configuring (406), by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information collected by the hypervisor; and enabling (408) the destination I/O adapter to recover from the error state.

The method of FIG. 7 differs from the method of FIG. 4 in that the method of FIG. 7 includes various alternatives for initiating the switch between I/O adapters for the logical partition. For example, the method of FIG. 7 includes receiving (702), by the management console from a user, a request to migrate from the source I/O adapter to the destination I/O adapter and administering (704), by the management console, migration from the source I/O adapter to the destination I/O adapter. The management console may provide a user interface through which a user may instruct the management console on various management operations of logical partitions. One such management operation may be switching the I/O adapter of the logical partition amongst adapters of the computing system. In this example, the management console may receive a user instruction through the user interface to migrate the source I/O adapter to the destination I/O adapter.

Administering (704) the migration from the source I/O adapter to the destination I/O adapter include communicating with the hypervisor to initiate the migration and orchestrating the migration after particular steps. For example, migrating (406) from the source I/O adapter to the destination I/O adapter may include instructing the hypervisor to collect the MMIO mapping information for the source I/O adapter, instructing the hypervisor to pause the destination I/O adapter through use of an error state, instructing the hypervisor to configure the MMU for MMIO between the logical partition and destination I/O adapter, and instructing the hypervisor to enable the destination I/O adapter to recover from the error state.

To that end, the method of FIG. 7 also includes notifying (706), by the hypervisor, the management console that migration has completed. Such a notification may then be passed along to a user that initiated the migration procedures or logged.

In other embodiments, the migration may be initiated, not by user direction or the management console, but dynamically in response to various conditions. To that end, the method of FIG. 7 also includes initiating (708), by the hypervisor, migration of from the source I/O adapter to the destination I/O adapter in response to one or more conditions. Such conditions may include failover conditions, workload balancing conditions, power consumption conditions, timing conditions, resource distribution conditions, and the like. In such an example, the hypervisor may be provided with a set of rules that specify migration between I/O adapters to be carried out when such conditions are met.

The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.

The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.

Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

It will be understood from the foregoing description that modifications and changes may be made in various embodiments of the present invention without departing from its true spirit. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present invention is limited only by the language of the following claims. 

What is claimed is:
 1. A method of migrating memory mapped input/output (‘MMIO’) from a source input/output (‘I/O’) adapter of a computing system to a destination I/O adapter of the computing system, the method comprising: placing, by a hypervisor of the computing system, the destination I/O adapter in an error state, wherein the hypervisor supports operation of a logical partition (‘LPAR’) and the logical partition is configured for MMIO operations with the source I/O adapter through a memory management unit (‘MMU’) utilizing MMIO mapping information; configuring, by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information; and enabling the destination I/O adapter to recover from the error state.
 2. The method of claim 1 wherein the source I/O adapter comprises a Peripheral Component Interconnect (‘PCI’) adapter and the method further comprises collecting the MMIO mapping information including: collecting a PCI configuration space address of the source I/O adapter; collecting a PCI memory address of the source I/O adapter; and collecting, from a hardware page table of a memory management unit (‘MMU’) of the computing system, LPAR logical memory addresses mapped to physical real addresses for MMIO.
 3. The method of claim 1 wherein: the source and destination I/O adapters comprise Peripheral Component Interconnect (‘PCI’) adapters; the method further comprises collecting physical real addresses utilized to route MMIO operations to memory space of the destination I/O adapter; and configuring, by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information further comprises: inserting, in a hardware page table of the MMU, mappings of the LPAR logical memory addresses to the physical real addresses utilized to route MMIO operations to memory space of the destination I/O adapter.
 4. The method of claim 1 further comprising: placing, by the hypervisor, the source I/O adapter in an error state, thereby quiescing MIMIO traffic to the source I/O adapter.
 5. The method of claim 1 further comprising: deconfiguring the source I/O adapter from the computing system.
 6. The method of claim 1 wherein a management console is coupled to the computing system and the method further comprises administering, by the management console, migration from the source I/O adapter to the destination I/O adapter.
 7. The method of claim 6 further comprising: notifying, by the hypervisor, the management console that migration has completed.
 8. The method of claim 6 further comprising: receiving, by the management console from a user, a request to migrate from the source I/O adapter to the destination I/O adapter.
 9. The method of claim 1 further comprising: initiating, by the hypervisor, migration of from the source I/O adapter to the destination I/O adapter in response to one or more conditions.
 10. An apparatus for migrating memory mapped input/output (‘MMIO’) from a source input/output (‘I/O’) adapter of a computing system to a destination I/O adapter of the computing system, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of: placing, by a hypervisor of the computing system, the destination I/O adapter in an error state, wherein the hypervisor supports operation of a logical partition (‘LPAR’) and the logical partition is configured for MMIO operations with the source I/O adapter through a memory management unit (‘MMU’) utilizing MMIO mapping information; configuring, by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information; and enabling the destination I/O adapter to recover from the error state.
 11. The apparatus of claim 10 wherein the source I/O adapter comprises a Peripheral Component Interconnect (‘PCI’) adapter and the apparatus further comprises computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the step of collecting the MMIO mapping information including: collecting a PCI configuration space address of the source I/O adapter; collecting a PCI memory address of the source I/O adapter; and collecting, from a hardware page table of a memory management unit (‘MMU’) of the computing system, LPAR logical memory addresses mapped to physical real addresses for MMIO.
 12. The apparatus of claim 10 wherein: the source and destination I/O adapters comprise Peripheral Component Interconnect (‘PCI’) adapters; the apparatus further comprises computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the step of collecting physical real addresses utilized to route MMIO operations to memory space of the destination I/O adapter; and configuring, by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information further comprises: inserting, in a hardware page table of the MMU, mappings of the LPAR logical memory addresses to the physical real addresses utilized to route MMIO operations to memory space of the destination I/O adapter.
 13. The apparatus of claim 10 further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the step of: placing, by the hypervisor, the source I/O adapter in an error state, thereby quiescing MMIO traffic to the source I/O adapter.
 14. The apparatus of claim 10 further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the step of: deconfiguring the source I/O adapter from the computing system.
 15. The apparatus of claim 10 wherein a management console is coupled to the computing system and the apparatus further comprises computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the step of administering, by the management console, migration from the source I/O adapter to the destination I/O adapter.
 16. A computer program product for migrating memory mapped input/output (‘MMIO’) from a source input/output (‘I/O’) adapter of a computing system to a destination I/O adapter of the computing system, the computer program product disposed upon a non-transitory, computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of: placing, by a hypervisor of the computing system, the destination I/O adapter in an error state, wherein the hypervisor supports operation of a logical partition (‘LPAR’) and the logical partition is configured for MMIO operations with the source I/O adapter through a memory management unit (‘MMU’) utilizing MMIO mapping information; configuring, by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information; and enabling the destination I/O adapter to recover from the error state.
 17. The computer program product of claim 16 wherein the source I/O adapter comprises a Peripheral Component Interconnect (‘PCI’) adapter and the computer program product further comprises computer program instructions that, when executed, cause the computer to carry out the step of collecting the MMIO mapping information including: collecting a PCI configuration space address of the source I/O adapter; collecting a PCI memory address of the source I/O adapter; and collecting, from a hardware page table of a memory management unit (‘MMU’) of the computing system, LPAR logical memory addresses mapped to physical real addresses for MMIO.
 18. The computer program product of claim 16 wherein: the source and destination I/O adapters comprise Peripheral Component Interconnect (‘PCI’) adapters; the computer program product further comprises computer program instructions that, when executed, cause the computer to carry out the step of collecting physical real addresses utilized to route MMIO operations to memory space of the destination I/O adapter; and configuring, by the hypervisor, the MMU for MMIO between the logical partition and the destination I/O adapter utilizing the MMIO mapping information further comprises: inserting, in a hardware page table of the MMU, mappings of the LPAR logical memory addresses to the physical real addresses utilized to route MMIO operations to memory space of the destination I/O adapter.
 19. The computer program product of claim 16 further comprising computer program instructions that, when executed, cause the computer to carry out the step of: placing, by the hypervisor, the source I/O adapter in an error state, thereby quiescing MMIO traffic to the source I/O adapter.
 20. The computer program product of claim 16 further comprising computer program instructions that, when executed, cause the computer to carry out the step of: deconfiguring the source I/O adapter from the computing system. 